50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. 50GbE Quick Start Guide 2. Design Example Description 3. Document Revision History
1. 50GbE Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 50GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 50GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 50GbE Design Example Registers
1. 50GbE Quick Start Guide
2. Design Example Description
3. Document Revision History

1.2. Simulation Design Example Components

Figure 3.  50GbE Simulation Design Example Block Diagram

The simulation example design top-level test file is basic_avl_tb_top.sv This file instantiates and connects an ATX PLL. It includes a task, send_packets_50g_avl, to send and receive 10 packets.

Table 1.   50GbE IP Core Testbench File Descriptions
File Name Description
Testbench and Simulation Files
basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
run_vsim.do The ModelSim script to run the testbench.
run_vcs.sh The Synopsys VCS script to run the testbench.
run_ncsim.sh The Cadence NCSim script to run the testbench.
run_xcelium.sh The Cadence Xcelium* script to run the testbench.
Level Two Title