50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. 50GbE Quick Start Guide 2. Design Example Description 3. Document Revision History
1. 50GbE Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 50GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 50GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 50GbE Design Example Registers
1. 50GbE Quick Start Guide
2. Design Example Description
3. Document Revision History

1.3. Hardware Design Example Components

Figure 4.  50GbE Hardware Design Example High Level Block Diagram
The 50GbE hardware design example includes the following components:
  • 50GbE IP core.
  • Client logic that coordinates the programming of the IP core and packet generation.
  • ATX PLL to drive the device transceiver channels.
  • IOPLL to generate a 100 MHz clock from a 50 MHz input clock to the hardware design example.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through the System Console.
Table 2.   50GbE IP Core Hardware Design Example File Descriptions

File Names

Description

eth_ex_50g.qpf Quartus Prime project file
eth_ex_50g.qsf Quartus project settings file
eth_ex_50g.sdc Synopsys Design Constraints file. You can copy and modify this file for your own 50GbE design.
eth_ex_50g.v Top-level Verilog HDL design example file
common/ Hardware design example support files
hwtest/main.tcl

Main file for accessing System Console
Level Two Title