50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. 50GbE Quick Start Guide 2. Design Example Description 3. Document Revision History
1. 50GbE Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 50GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 50GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 50GbE Design Example Registers
1. 50GbE Quick Start Guide
2. Design Example Description
3. Document Revision History

2.3. 50GbE Design Example Registers

Table 5.   50GbE Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.

Word Offset

Register Category

0x300–0x5FF

 50GbE IP core registers.

0x4000–0x4C00

 Arria 10 dynamic reconfiguration registers. Register base address is 0x4000 for Lane 0 and 0x4400 for Lane 1.
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