50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
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2.3. 50GbE Design Example Registers

Table 5.   50GbE Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console.

Word Offset

Register Category

0x300–0x5FF

 50GbE IP core registers.

0x4000–0x4C00

 Arria 10 dynamic reconfiguration registers. Register base address is 0x4000 for Lane 0 and 0x4400 for Lane 1.
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