1.6. Compiling and Configuring the Design Example in Hardware
To compile the hardware design example and configure it on your Arria 10 GT device, follow these steps:
- Ensure hardware design example generation is complete.
- In the Intel® Quartus® Prime software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_50g.qpf.
- Before compiling, ensure you have implemented the workaround from the KDB Answer How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? if relevant for your software release.
- On the Processing menu, click Start Compilation.
- After you generate a SRAM object file .sof, follow these steps to program the hardware design example on the Arria 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Arria 10 GT board with 25G retimer to your Intel® Quartus® Prime session.
- Ensure that Mode is set to JTAG.
- Select the Arria 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
Note: This design example targets the Arria 10 GT device. Please contact your Intel FPGA representative to inquire about a platform suitable to run this hardware example
Did you find the information on this page useful?