50G Ethernet Design Example User Guide

ID 683350
Date 4/03/2019
Public
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1. 50GbE Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 17.0

The 50GbE IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled hardware design to an Arria 10 GT device.

Note: This design example targets the Arria 10 GT device and requires a 25G retimer. Please contact your Intel FPGA representative to inquire about a platform suitable to run this hardware example. In some cases a loan of appropriate hardware may be available.

In addition, Intel provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Figure 1. Design Example Usage

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