50G Ethernet Design Example User Guide

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ID 683350
Date 4/03/2019
Public
Document Table of Contents
Document Table of Contents x
1. 50GbE Quick Start Guide 2. Design Example Description 3. Document Revision History
1. 50GbE Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design Example 1.5. Simulating the 50GbE Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the 50GbE Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Design Example Interface Signals 2.3. 50GbE Design Example Registers
1. 50GbE Quick Start Guide
2. Design Example Description
3. Document Revision History

3. Document Revision History

Table 6.  50G Ethernet Design Example User Guide Revision History
Date Release Changes
2019.04.03 17.0 Added the command to run Xcelium simulations.
2017.11.08 17.0 Added link to KDB Answer that provides workaround for potential jitter on Intel® Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Generating the Design Example and Compiling and Configuring the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Intel® Quartus® Prime releases later than the Intel® Quartus® Prime software release v17.0.
2017.05.08 17.0 Initial public release.
Level Two Title