3. Document Revision History
|2019.04.03||17.0||Added the command to run Xcelium simulations.|
|2017.11.08||17.0||Added link to KDB Answer that provides workaround for potential jitter on Intel® Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Generating the Design Example and Compiling and Configuring the Design Example in Hardware.
Note: This design example user guide has not been updated to reflect minor changes in design generation in Intel® Quartus® Prime releases later than the Intel® Quartus® Prime software release v17.0.
|2017.05.08||17.0||Initial public release.|
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