Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Document Table of Contents

1. Serial Lite III Streaming Intel® FPGA IP Quick Reference

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 20.1.0

The Serial Lite III Streaming Intel® FPGA IP core is a lightweight protocol suitable for high bandwidth streaming data in chip-to-chip, board-to-board, and backplane applications.

Table 1.   Serial Lite III Streaming Intel® FPGA IP



Release Information


24.1 Quartus® Prime Pro Edition ( Stratix® 10, Arria® 10, and Cyclone® 10 GX devices)

21.1 Quartus® Prime Standard Edition ( Arria® 10, Stratix® V, and Arria® V GZ devices)

Release Date

April 2024 ( Quartus® Prime Pro Edition v24.1)

November 2021 ( Quartus® Prime Standard Edition v21.1)

IP Catalog Name
  • Serial Lite III Streaming Intel® FPGA IP ( Stratix® 10, Stratix® V, and Arria® V GZ devices)
  • Serial Lite III Streaming Arria® 10 FPGA IP
  • Serial Lite III Streaming Cyclone® 10 GX FPGA IP

Ordering Code


Product ID


Vendor ID


IP Information

Core Features

  • Up to 28 Gbps 1 lane data rate for Stratix® 10 with H-tile or E-tile transceivers.
  • Up to 17.4 Gbps lane data rates for Arria® 10 devices.
  • Supports 1–24 serial lanes in configurations that provide nominal bandwidths from 3.125 gigabits per second (Gbps) to over 400 Gbps.
  • Up to 12.5 Gbps for Cyclone® 10 GX devices.

Protocol Features

  • Source (simplex transmitter), sink (simplex receiver), and duplex operations
  • Support for single or multiple lanes
  • 64/67B physical layer encoding
  • Payload and idle scrambling
  • Error detection
  • Low overhead framing
  • Low point-to-point transfer latency

Typical Application

  • High resolution video
  • Radar processing
  • Medical imaging
  • Baseband processing in wireless infrastructure

Device Family Support

Stratix® 10 (Final support), Arria® 10 (Final support), Cyclone® 10 GX (Final support), Arria® V GZ (Final support), and Stratix® V (Final support) FPGA devices.

Advance support - The IP is available for simulation and compilation for this device family. FPGA programming file (.pof) support is not available for Quartus® Prime Pro – Stratix 10 Edition Beta software and as such IP timing closure cannot be guaranteed. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).

Final support - The IP is verified with final timing models for this device family. The IP meets all the functional and timing requirements for the device family and can be used in production designs.

Design Tools

  • IP parameter editor in the Quartus® Prime software for IP design instantiation and compilation
  • Timing Analyzer in the Quartus® Prime software for timing analysis
  • ModelSim* , QuestaSim* , MATLAB, or third-party tool using NativeLink for design simulation or synthesis