Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

7.2. Configuration and Status Registers

Table 48.  Source Configuration and Status Registers for MACUse the following definition for register access shown in the table:
  • W1C = Write 1 to clear.
  • RW = Read Write.
Word Address Bits Register Name Description

Access

 Default Value
TX MAC Status
0x0081 7:4 TXA_reentry_buffer

This field indicates the number of lane alignment re-entry.

RO 0x00
1 TXA_POSTFRAME_WAIT_entered This bit indicates the core is in TXA_POSTFRAME_WAIT state and only be cleared when the state machine enters IDLE state or reset. RO 0x0
0 TXA_FILL_entered This bit indicates the alignment state machine enters TXA_FILL state and only be cleared when the state machine enters IDLE state or reset. RO 0x0
TX Error Status Register
0x0090 6 tx_burst_gap_err

TX burst gap error.

This bit is set when the gap between two consecutive bursts (or packets) on TX user data interface is less than the required BURST_GAP (a synthesis option). When this error happens, make sure the user interface behavior and BURST_GAP are matching.

W1C

 0x0
5 ecc_err_fatal

TX ECC Error Fatal consolidated status (of all lanes).

This bit is set when double bit error is detected and uncorrected.

W1C

 0x0
4 ecc_err_corrected

TX ECC Error Corrected consolidated status (of all lanes).

This bit is set when single bit error is detected and corrected.

W1C

 0x0
3 adapt_fifo_overflow

TX MAC Adaptation FIFO overflow consolidated status (of all lanes).

In normal condition with all clocks running correctly, this bit is set when the user data rate is faster than expected.When this happens, stop further data transfer and check if the clocks are set correctly.

W1C

 0x0
2 tx_sync_done_lost

TX Lost of Lane Alignment consolidated status (of all lanes).

W1C

 0x0
1 phy_fifo_underflow

TX PHY Phase Compensation FIFO underflow consolidated status (of all lanes).

This bit is set when the IP core has major error and requires a full IP core reset.

W1C

 0x0
0 phy_fifo_overflow

TX PHY Phase Compensation FIFO overflow consolidated status (of all lanes).

This bit is set when the IP core has major error and requires a full IP core reset.

W1C

 0x0
TX Error Interrupt Enable Register
0x0091 6 tx_burst_gap_err_en

Set this bit to 1 to enable the Burst Gap Error Interrupt.

RW

 0x1
5 ecc_err_fatal_en

Set this bit to 1 to enable the ECC Uncorrected Error Interrupt.

RW

 0x0
4 ecc_err_corrected_en

Set this bit to 1 to enable the ECC Corrected Error Interrupt.

RW

 0x0
3 adapt_fifo_overflow_en

Set this bit to 1 to enable the Adaptation FIFO Overflow Interrupt.

RW

 0x1
2 tx_sync_donelost_en

Set this bit to 1 to enable the Loss of Lane Alignment Interrupt.

RW

 0x0
1 phy_fifo_underflow_en

Set this bit to 1 to enable the PHY FIFO Empty Interrupt.

RW

 0x0
0 phy_fifo_overflow_en

Set this bit to 1 to enable the PHY FIFO Error Interrupt.

RW

 0x0
Table 49.  Sink Configuration and Status Registers for MACUse the following definition for register access shown in the table:
  • W1C = Write 1 to clear.
  • RW = Read Write.
Word Address Bit Register Name Description Access Default Value
RX MAC Status
0x00C1 9 rx_aligned This bit set when sink core link is aligned successfully. RO 0x0
  8:2 LASM_misaligned_counter This field indicates the number of sink alignment retries. RO 0x00
  1 LASM_DESKEW_entered This bit is set to indicates sink alignment state machine is in LASM_DESKEW state and is only cleared when the state machine enters IDLE state or reset. RO 0x00
  0 LASM_FRAME_LOCK_entered This bit is set to indicates sink alignment state machine is in LASM_FRAME_LOCK state and is only cleared when the state machine enters IDLE state or reset. RO 0x00
RX MAC Control Register
0x00C2 0 link_reinit

Set this bit to initiate link re-initialization.

When asserted, lane alignment state machine goes to IDLE state and restart the lane alignment process.

RW

 0x0
RX Error Status Register
0x00D00 11 rx_data_err

RX Data Error.

This bit is set when the MAC receives data to transmit to user logic but ready_rx signal is de-asserted.

W1C 0x0
10 rx_deskew_fatal

RX Lane Deskew Fatal status (of all lanes).

This bit is set, when the lane skews across all lanes have exceeded the hardware de-skew capability. This should not happen under normal conditions. When this bit is set, identify the routing of the lanes (e.g. RX PHY-> board routing -> TX PHY) where large skews are introduced.

W1C

 0x0
9 ecc_err_fatal

RX ECC Error Fatal consolidated status (of all lanes).

This bit is set when double bit error detected and uncorrected.

W1C

 0x0
8 ecc_err_corrected

RX ECC Error Corrected consolidated status (of all lanes).

This bit is set when single bit error is detected and corrected.

W1C

 0x0
7 adapt_fifo_overflow

RX Adaptation FIFO Overflow

This bit is set when user data rate is slower than expected. When this bit is set, stop all data transfer. Verify clocks are set correctly, or verify if ready_rx signal is asserted correctly.

W1C 0x0
6 rx_alignment_lostlock

RX Lane Alignment Lost consolidated status (of all lanes).

This bit is set when lost of alignment is detected by the MAC. This error happens when the SYNC control words across all lanes do not appear in the same clock cycle and data corruption could have happened since one or more lanes would be out of alignment with others.

The RX MAC re-establishes the alignment to recover from this error. However, if the condition still persists, a full IP reset is required.

W1C

 0x0
5 rx_align_retry_fail

RX Lane Alignment Retry Fail consolidated status (of all lanes).

This bit is set to indicate the number of lane alignment retries has exceeded the expected value.

W1C

 0x0
4 rx_pcs_err

RX PCS Error consolidated status (of all lanes).

This bit is set when a synchronization error, metaframe error or crc32 error happens.

W1C

 0x0
3 rx_crc32err

RX CRC error consolidated status (of all lanes) for data integrity monitoring purpose.

W1C

 0x0
2 —

Reserved

 — —
1 rx_block_lostlock

RX Loss of Block Lock consolidated status (of all lanes).

This bit is set when there is a loss of block lock in the receive frame due to signal integrity errors on the serial data stream or when the remote partner is being reset.

When this happen, check and remove the cause of loss of block lock to enable the IP core to self-recover to normal state.

W1C

 0x0
0 phy_fifo_overflow

RX PHY Phase Compensation FIFO overflow consolidated status (of all lanes).

This bit is set when the IP core has major error and requires a full IP core reset.

W1C

 0x0
RX Error Interrupt Enable Register
0x00D1 11 rx_data_err_int_en

RX Data Error Enable

Set this bit to 1 to enable the RX Data Error Enable Interrupt.

RW 0x0
10 rx_deskew_fatal_int_en Set this bit to 1 to enable the RX Lane Deskew Fatal Interrupt.

RW

 0x0
9 ecc_err_fatal_int_en Set this bit to 1 to enable the RX ECC Error Detected and Uncorrected Interrupt. RW 0x0
8 ecc_err_corrected_int_en Set this bit to 1 to enable the RX ECC Error Detected and Corrected Interrupt. RW 0x0
7 adapt_fifo_over_flow_int_en

RX Adaptation FIFO Overflow Enable

Set this bit to 1 to enable the RX Adaptation FIFO Overflow Interrupt.

RW 0x0
6 rx_alignment_lostlock_int_en Set this bit to 1 to enable the RX Loss of Lane Alignment Interrupt. RW 0x0
5 rx_align_retry_fail_int_en Set this bit to 1 to enable the RX Lane Alignment Retry Fail Interrupt. RW 0x0
4 rx_pcs_err_int_en Set this bit to 1 to enable the RX PCS Error Interrupt. RW 0x0
3 rx_crc32err_int_en Set this bit to 1 to enable the RX CRC Error Interrupt. RW 0x0
2 — Reserved — —
1 rx_block_lostlock_int_en Set this bit to 1 to enable the RX Loss of Block Lock Interrupt. RW 0x0
0 phy_fifo_overflow_int_en Set this bit to 1 to enable the RX PHY FIFO Overflow Interrupt. RW 0x0
Table 50.  Interlaken PHY Registers
Word Addr Bits R/W Register Name Description
PMA Common Control and Status Registers
0x022 [<p>-1:0] RO pma_tx_pll_is_locked If < p > is the PLL number, Bit[< p >] indicates that the TX CMU PLL (< p >) is locked to the input reference clock. There is typically one pma_tx_pll_is_locked bit per system.
Reset Control Registers-Automatic Reset Controller
0x041 [31:0] RW reset_ch_bitmask

Reset controller channel bitmask for digital resets. The default value is all 1s. Channel <n> can be reset when bit< n > = 1. Channel < n > cannot be reset when bit< n > = 0.

The Interlaken PHY IP requires the use of the embedded reset controller to initiate the correct the reset sequence. A hard reset to phy_mgmt_clk_reset and mgmt_rst_reset is required for Interlaken PHY IP.

Intel does not recommend use of a soft reset or the use of these reset register bits for Interlaken PHY IP.

0x042 [1:0] WO reset_control (write) Writing a 1 to bit 0 initiates a TX digital reset using the reset controller module. The reset affects channels enabled in the reset_ch_bitmask. Writing a 1 to bit 1 initiates a RX digital reset of channels enabled in the reset_ch_bitmask.
RO reset_status(read) Reading bit 0 returns the status of the reset controller TX ready bit. Reading bit 1 returns the status of the reset controller RX ready bit.
Reset Controls -Manual Mode
0x044 - RW reset_fine_control

You can use the reset_fine_control register to create your own reset sequence. The reset control module, illustrated in Transceiver PHY Top-Level Modules, performs a standard reset sequence at power on and whenever the phy_mgmt_clk_reset is asserted. Bits [31:4, 0] are reserved.

The Interlaken PHY IP requires the use of the embedded reset controller to initiate the correct the reset sequence. A hard reset to phy_mgmt_clk_reset and mgmt_rst_reset is required for Interlaken PHY IP.

Intel does not recommend use of a soft reset or the use of these reset register bits for Interlaken PHY IP.

[3] RW reset_rx_digital Writing a 1 causes the RX digital reset signal to be asserted, resetting the RX digital channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[2] RW reset_rx_analog Writing a 1 causes the internal RX digital reset signal to be asserted, resetting the RX analog logic of all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
[1] RW reset_tx_digital Writing a 1 causes the internal TX digital reset signal to be asserted, resetting all channels enabled in reset_ch_bitmask. You must write a 0 to clear the reset condition.
PMA Control and Status Registers
0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel < n > puts channel < n > in tx to rx serial loopback mode. For information about pre- or post-CDR rx to tx serial loopback modes, refer to Loopback Modes.
0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to lock to the incoming data. Bit < n > corresponds to channel < n >. By default, the Interlaken PHY IP configures the CDR PLL in Auto lock Mode. This bit is part of the CDR PLL Manual Lock Mode which is not the recommended usage.
0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to lock to the reference clock. Bit < n > corresponds to channel < n >. By default, the Interlaken PHY IP configures the CDR PLL in Auto lock Mode. This bit is part of the CDR PLL Manual Lock Mode which is not the recommended usage.
0x066 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR PLL is locked to the RX data, and that the RX CDR has changed from LTR to LTD mode. Bit < n > corresponds to channel < n >.
00x067 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit < n > corresponds to channel < n >.
0x080 [31:0] WO indirect_addr Provides for indirect addressing of all PCS control and status registers. Use this register to specify the logical channel address of the PCS channel you want to access.
Device Registers
[27] RO rx_crc32_err

Asserted by the CRC32 checker to indicate a CRC error in the corresponding RX lane.

From block: CRC32 checker.

0x081 [25] RO rx_sync_lock

Asserted by the frame synchronizer to indicate that 4 frame synchronization words have been received so that the RX lane is synchronized.

From block: Frame synchronizer.

[24] RO rx_word_lock

Asserted when the first alignment pattern is found. The RX FIFO generates this synchronous signal.

From block: The RX FIFO generates this synchronous signal.

For Native PHY IP core configuration and status registers, refer to Arria® 10 Transceiver Register Map, Logical View of the Stratix® 10 L-Tile/H-Tile Transceiver Registers, and Stratix® 10 E-Tile Transceiver PHY User Guide Register Map in related links.

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