Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 11/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming IP Quick Reference 2. About the Serial Lite III Streaming IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming IP Functional Description 6. Serial Lite III Streaming IP Clocking Guidelines 7. Serial Lite III Streaming IP Configuration and Status Registers 8. Serial Lite III Streaming IP Debugging Guidelines 9. Serial Lite III Streaming IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming IP User Guide
2. About the Serial Lite III Streaming IP x
2.1. Serial Lite III Streaming IP Protocol 2.2. Serial Lite III Streaming IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing IPs 3.2. IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. IP Evaluation Mode x
3.2.1. Altera® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming IP Link Debugging
8.2. Serial Lite III Streaming IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming IP Quick Reference
2. About the Serial Lite III Streaming IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming IP Functional Description
6. Serial Lite III Streaming IP Clocking Guidelines
7. Serial Lite III Streaming IP Configuration and Status Registers
8. Serial Lite III Streaming IP Debugging Guidelines
9. Serial Lite III Streaming IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming IP User Guide

5.10. Accessing Configuration and Status Registers

The Avalon memory-mapped PHY management block within the Interlaken PHY IP core or Native PHY IP core includes master and slave interfaces. This component acts as a bridge. It transfers commands received on its Avalon memory-mapped slave interface to its Avalon memory-mapped port. This interface manages PCS and PMA modules, resets, error handling, and serial loopback controls. Refer to Configuration and Status Registers for more information of registers that you can access using the Avalon memory-mapped PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers.

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