Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Document Table of Contents

5.1.1. Serial Lite III Streaming Source Core

The source core consists of four major functional blocks (the implementation varies depending on the clocking mode):

  • Source application module
  • Source adaptation module
  • L-Tile/H-Tile Transceiver Native PHY Stratix® 10 FPGA IP and Transceiver Native PHY IP TX core for Arria® 10 and Cyclone® 10 GX - Interlaken mode
  • Interlaken PHY v18.1 IP TX core ( Stratix® V and Arria® V GZ devices)
  • Clock generator (in the standard clocking mode for Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ devices)