Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Document Table of Contents

3.4.1. Parameters

Table 10.   Serial Lite III Streaming Intel® FPGA IP Parameter Description
Parameter Value Default Description
General Design Options


Duplex, Tx, Rx


Select the variation of the IP.

Number of lanes


1 Specifies the number of lanes.

Meta frame length in words

200–8191 200

Specifies the metaframe length.

Transceiver reference clock frequency <Range supported by the transceiver PLLs> 175.0 MHz Specifies the reference clock frequency of the transceiver.
System PLL frequency 875.0 875.0 Specifies the system PLL frequency.
Enable M20K ECC support Yes/No No Select to use error correcting code (ECC) protection to strengthen the FIFO buffers from single-event upset (SEU) changes. Enables built-in error correcting code (ECC) support on the M20K embedded block memory for single-error correction, double-adjacent-error correction, and triple-adjacent-error detection.
Transceiver Type FGT FGT Selects the transceiver type.
User Interface
Streaming Mode



FULL Specifies the streaming mode.
  • BASIC: This is a pure streaming mode where data is sent without burst, sync, empty cycle, and frame delimiter to increase bandwidth.
  • FULL: This mode sends a burst and sync cycle at the start of frame and a burst and empty cycle at the end of frame. Provide a gap of one empty cycle between two data frames.
Required idle cycles between bursts 1, 2 2 Supports two values to optimize for bandwidth efficiency or maintain backward compatibility with existing Serial Lite III Streaming IPs (legacy).
  • 1: Recommended for high bandwidth streaming. The same Burst Gap setting must be set for both TX and RX IP cores.
  • 2: For backward compatibility with Quartus II software version 15.1 and older RX IP core.
Adaptation FIFO partial full threshold 8 - 18 15

Specifies the partial full threshold of the transmit FIFO. The ready_tx signal deasserts when data reaches this level in the FIFO.

Clocking mode

Standard clocking mode,

Advanced clocking mode

Standard clocking mode

Specifies the clocking mode.

Refer to Serial Lite III Streaming Intel FPGA IP Clocking Guidelines for more information.

User input

User clock frequency,

Transceiver data rate

User clock frequency

Select User clock frequency to specify the user clock input and allow the IP to determine the transceiver data rate.

Select Transceiver data rate to specify the desired data rate and allow the IP to determine the user clock frequency.

User clock frequency required

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

177.556818 MHz

Specifies the desired frequency for the user clock input for the transmit (Standard Clocking Mode and Advanced Clocking Mode) and receive user interface (Standard Clocking Mode).

This frequency in turn determines the required transceiver data rate to support the calculated transmit and receive bandwidths.

Transceiver data rate

required user clock frequency * overheads * 64

12.5 Gbps

The effective data rate at the output of the transceivers, incorporating transmission and other overheads.

The parameter editor automatically calculates this value by adding the input data rate with transmission overheads to provide you with a selection of user clock frequency.

Aggregate user bandwidth

number of lanes * required user clock frequency * 64

68.18 Gbps

This value is derived by multiplying the number of lanes and user interface data rate.