Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Document Table of Contents

3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs

If your design targets Stratix® V or Arria® V GZ devices, the transceiver reconfiguration controller is not included in the generated IP. To create a complete system, refer to the design example block diagram on how to connect the transceiver reconfiguration controller.

Note: If your design targets Arria® 10, Cyclone® 10 GX and Stratix® 10 devices, the transceiver reconfiguration functionality is embedded inside the transceivers. The phy_mgmt bus interface connects directly to the Avalon® memory-mapped dynamic reconfiguration interface of the embedded Arria® 10, Cyclone® 10 GX and Stratix® 10 Native PHY IP. This interface is provided at the top level. For Quartus compilation design, create clock constraints for the phy_mgmt_clk and reconfig_to_xcvr[0] (for Stratix® V and Arria® V GZ) signals to avoid unconstrained clock warnings.