Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Document Table of Contents

5.6. CRC-32 Error Injection

In the Quartus® Prime software version 13.1 and later, the Serial Lite III Streaming IP core supports CRC error injection with the 10G PCS CRC-32 generator. This feature enables corruption of the CRC-32 value of the CRC-32 generator.

To insert CRC errors for a given lane, the IP interface includes a CRC error injection control signal. Asserting this control signal inserts CRC errors for all the lanes and transceivers that have enabled support for error injection. You can enable the CRC error injection for a specific transceiver channel (Serial Lite III Streaming lane) by programming the appropriate transceiver PCS CRAM bit. The provided example design demonstrates how set the respective CRAM bits using the Nios® V processor.

For proper functionality of this feature, you must verify that you are adhering to the following steps:
  1. Verify both link_up_tx and link_up_rx are asserted.
  2. Verify the user can send/receive normal traffic.
  3. After link up, program the transceiver register and verify the register bit (PCS CRAM bit) by reading.
  4. With link up, toggle crc_error_inject port to high on the transmitter.
  5. Monitor the error_rx output on the receiver.