The SDI II IP core.

Channel 0 TX/RX—the instance of the SDI II IP in this channel is configured in simplex TX/RX mode to support SD-SDI, HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI.

Channel 0 of the SDI RX receives external SDI video data from the BNC port through the transceiver RX pin.

For more information, refer to Channel Data Rate.

The Arria 10 fPLL IP core. This reference design uses an fPLL core as the TX PLL for the Arria 10 Transceiver Native PHY IP.

This IP core uses 297/296.7 MHz frequency derived from the Nextera FMC daughter card as a reference clock.

The Altera Arria 10 Transceiver Native PHY IP core. The reference design uses this PHY IP to configure the transceiver PHY for the SDI II protocol implementation. You can select the preset settings for the PHY IP core defined for the SDI II protocol. To apply a preset to the PHY IP core, double click the preset name. When you apply a preset, the PHY parameters are set accordingly for the instance.

The Altera Transceiver PHY Reset Controller IP core. This reset controller handles the sequencing of the transceiver reset. Depending on the status received from the TX transceiver PHY, TX PLL, TX reset input, or the RX transceiver PHY or the SDI asynchronous reset output signal, the reset controller generates the TX or RX reset signals to the TX/RX transceiver PHY, SDI, and TX PLL.

This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out. The receiver sends the decoded RX data to the transmitter through this FIFO buffer. When the receiver is locked, the RX data is written to the FIFO buffer. The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.

This block contains a state machine that performs the transceiver reconfiguration process. The Avalon-MM reconfiguration interface of this block is connected to the Arria 10 Transceiver Native PHY for the reconfiguration of the SDI II IP core. Although this block supports both TX and RX reconfiguration, this reference design only implements RX reconfiguration.

A simple logic to generate a slow clock and display on the LEDs.