AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

ID 683319
Date 5/08/2017
Public

1.2.1. Receiver

To run the test, connect an SDI signal generator to the receiver input, SDI_IN (J1), of channel 0.

This test uses the following user LEDs to indicate the respective conditions:
  • D8, D9, and D10 indicate the receiver signal standard.
  • D7 illuminates when the CRC error signal for channel 0 is asserted.
  • D6 illuminates when the trs_locked signal for channel 0 is asserted.
  • D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 5. User LEDs