AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

ID 683319
Date 5/08/2017
Public

1.2.2. Parallel Loopback

Follow these steps to run the parallel loopback test:

  1. Connect an SDI signal generator to the receiver input, SDI_IN (J1), of channel 0.
  2. Connect an SDI signal analyzer to the transmitter output, SDI_OUT (J2), of channel 0.
  3. Check the result on the SDI signal analyzer.
This test uses the following user LEDs to indicate the respective conditions:
  • D8, D9, and D10 indicate the receiver signal standard.
  • D7 illuminates when the CRC error signal for channel 0 is asserted.
  • D6 illuminates when the trs_locked signal for channel 0 is asserted.
  • D5 illuminates when the frame_locked signal for channel 0 is asserted.
Figure 6. User LEDs


Note: LMH1983 does not support 1080 p48 format. For more details, refer to the Texas Instrument LMH1983 Datasheet.