AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

ID 683319
Date 5/08/2017

1.4. Compiling the Design and Configuring the FPGA

You must compile the design before you can configure the FPGA. Because the design is volatile, you must reload the design each time you power on the board.
Follow these steps to compile the design and configure the Arria 10 device:
  1. To test the reference designs targeted on Arria 10 device, download the reference design file to your local project directory:
    Arria 10 Multi Rate (Up to 12G) SDI II with External VCXO Reference Design: sdi_mr_a10_vcxo_an768.par
  2. Launch the Quartus® Prime software.
  3. On the File menu, click New Project Wizard.
  4. On the New Project Wizard page, open Design Template Installation. Select the design template you want to install. Click Next, then Finish.
  5. On the Processing menu, click Start Compilation.
  6. Before you begin the FPGA configuration, ensure that the Quartus® Prime Programmer and the Intel® FPGA Download Cable II driver are installed on the host computer, the board is powered, and no other applications that use the JTAG chain are running.
  7. Connect the USB cable to the board.
  8. On the Tools menu, click Programmer.
  9. Click Auto Detect to display the devices in the JTAG chain and select a device.
  10. Right click and select Change File. Then, select the appropriate .sof file from the project directory and click Open.
  11. Turn on the Program/Configure option for the .sof file.
  12. Click Start to download the .sof file to the FPGA. Configuration is complete when the progress bar reaches 100%.