AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

ID 683319
Date 5/08/2017

1.3.1. Channel Data Rate

Based on the input detected by the video standard, this reference design reconfigures the RX transceiver channel's data rate and personal communications system (PCS) data width.
Table 7.  RX Transceiver Channel Data Rate and PCS Data Width
Video Standard PCS-PLD Data Width Transceiver Data Rate (Gbps)
SD-SDI 20 2.970 2
HD-SDI 20 1.485 or 1.4835
3G-SDI 20 2.970 or 2.967
6G-SDI 40 5.940 or 5.934
12G-SDI 80 11.880 or 11.868
Based on the standard of the SDI video data received, the SDI II RX core divides the parallel data into one, two, or four 20-bit data streams.
Table 8.  Data Streams for Different Video Standards
Video Standards Data Stream
6G-SDI 2
12G-SDI 4

In this reference design, the video data from Channel 0 RX —in four 20-bit data streams —are looped back internally to Channel 0 TX for retransmission.. This channel demonstrates a receiver-to-transmitter loopback by decoding, buffering, and retransmitting the received video data to be displayed on the scope. The SDI II RX core uses an external clock of 148.5 or 148.35 MHz.

2 11 times oversampling for receiving SD-SDI.