AN 768: Multi-Rate (Up to 12G) SDI II Reference Design for Intel® Arria® 10 Devices

ID 683319
Date 5/08/2017

1.2. Running the Multi Rate (Up to 12G) SDI II with External VCXO Reference Design

When the board is set up and the FPGA is configured, you can start running the demonstration tests. Subsequent topics describe the tests that you can run.
Table 5.  User LEDsThe User LEDs indicate the expected results. A logical 1 indicates that the LED illuminates, a logical 0 indicates otherwise.
User LEDs Description
D3 The heartbeat of the transmitter clock out for channel 0.
D4 The heartbeat of the receiver recovered clock out for channel 0.
D5 Frame locked for channel 0.
D6 TRS locked for channel 0.
D7 CRC error on Chroma/Luma for channel 0.

Applicable for all modes except SD-SDI.

D8–D10 RX signal standard for channel 0:
  • SD: [D8, D9, D10] = 000
  • HD: [D8, D9, D10] = 001
  • 3Gb: [D8, D9, D10] = 010
  • 3Ga: [D8, D9, D10] = 011
  • 6Gb: [D8, D9, D10] = 100
  • 6Ga: [D8, D9, D10] = 101
  • 12Gb: [D8, D9, D10] = 110
  • 12Ga: [D8, D9, D10] = 111
Note: You need to compile and configure the design before you run the tests. For more information about compiling and configuring the design, refer to Compiling the Design and Configuring the FPGA.


You may reset the reference design by pressing the S4 push button on the development board.