AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

ID 683317
Date 6/08/2022

1.4.2. JESD204B Subsystem Overview

Figure 16. JESD204B Subsystem Diagram


Device_clock uses the serializer/deserializer (SERDES) dedicated reference pin. As such, the IOPLL cannot replace the fPLL, as shown in Figure 16.

Because Device_clock is not stable before programming the FPGA image, you must recalibrate the fPLL, ATX PLL, and SERDES TX and RX after configuring the ADI ADRV9029 Sub6G EBZ board. Otherwise, the fPLL and ATX PLL may not be locked. To recalibrate these elements, enable the dynamic reconfiguration plus capability and control and status registers of fPLL and JESD204B Intel® FPGA IP, as shown in Figure 17.

System Console or NIOS

This demo project uses the Intel® Arria® 10 SoC HPS to control the system.

JESD204B Intel® FPGA IP and Example Project Setting

Figure 17. JESD204B Intel® FPGA IP Setting: Main Tab
Figure 18. JESD204B Intel® FPGA IP Setting: JESD204B Configurations Tab
Figure 19. JESD204B Intel® FPGA IP Example Design Project Setting

Replacing core_PLL with fPLL

Use fPLL to replace the core_PLL if the reference clock is supplied from the SERDES dedicated reference clock pin.

Figure 20. Example Project – IOPLL
Figure 21. Example – fPLL Replacing IOPLL


The JESD204B TX in the ADI ADRV9029 Sub6G EBZ board requires sync_n from the Intel® Arria® 10 SoC board.