AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

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ID 683317
Date 6/08/2022
Public
Document Table of Contents
Document Table of Contents x
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board x
1.1. Introduction 1.2. Hardware and Software Requirements 1.3. Hardware Design 1.4. Functional Description 1.5. Reference Design 1.6. Document Revision History for AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board 1.7. Appendix
1.4. Functional Description x
1.4.1. DFE Processing in FPGA 1.4.2. JESD204B Subsystem Overview Device_clock System Console or NIOS JESD204B Intel® FPGA IP and Example Project Setting Replacing core_PLL with fPLL Sync_n_out
1.5. Reference Design x
1.5.1. Design Files 1.5.2. Running the Demo with Prebuilt Binaries 1.5.3. Enable Loopback 1.5.4. Configuration Registers
1.5.2. Running the Demo with Prebuilt Binaries x
1.5.2.1. Bringing Up Demo System Using SD Card Image
1.5.2.1. Bringing Up Demo System Using SD Card Image x
1.5.2.1.1. Creating SD Card 1.5.2.1.2. Configuring the Board 1.5.2.1.3. Running the Demo
1.5.4. Configuration Registers x
1.5.4.1. Address Map 1.5.4.2. Status Registers 1.5.4.3. Control Registers 1.5.4.4. PLL Status Registers 1.5.4.5. Base_address_sample_control Registers
1.5.4.1. Address Map x
1.5.4.1.1. Cortex-A9 MPU Address Maps
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

1.4.2. JESD204B Subsystem Overview

Figure 16. JESD204B Subsystem Diagram

Device_clock

Device_clock uses the serializer/deserializer (SERDES) dedicated reference pin. As such, the IOPLL cannot replace the fPLL, as shown in Figure 16.

Because Device_clock is not stable before programming the FPGA image, you must recalibrate the fPLL, ATX PLL, and SERDES TX and RX after configuring the ADI ADRV9029 Sub6G EBZ board. Otherwise, the fPLL and ATX PLL may not be locked. To recalibrate these elements, enable the dynamic reconfiguration plus capability and control and status registers of fPLL and JESD204B Intel® FPGA IP, as shown in Figure 17.

System Console or NIOS

This demo project uses the Intel® Arria® 10 SoC HPS to control the system.

JESD204B Intel® FPGA IP and Example Project Setting

Figure 17. JESD204B Intel® FPGA IP Setting: Main Tab
Figure 18. JESD204B Intel® FPGA IP Setting: JESD204B Configurations Tab
Figure 19. JESD204B Intel® FPGA IP Example Design Project Setting

Replacing core_PLL with fPLL

Use fPLL to replace the core_PLL if the reference clock is supplied from the SERDES dedicated reference clock pin.

Figure 20. Example Project – IOPLL
Figure 21. Example – fPLL Replacing IOPLL

Sync_n_out

The JESD204B TX in the ADI ADRV9029 Sub6G EBZ board requires sync_n from the Intel® Arria® 10 SoC board.

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