AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

ID 683317
Date 6/08/2022
Public Control Registers

Table 5.  Status RegisterAddress: 0xff218020
Bit Register Name Description Attribute Reset Value
31 sysref Generates the sysref for loopback test. WR 1’b0
30 hw_rst Global reset from register. WR 1’b0
24 Xcvr_rst
  • 1: Reset
  • 0: Deassert
WR 1’b0
23:8 Gain_control Tx data gain value. N/A N/A
7 N/A N/A N/A N/A
[6:4] Tx data mode
  • 3’d0: Turn off
  • 3’d1: Single tone out
  • 3’d2: 100 MHz data out
  • 3’d3: Gain out
  • 3’d4: Increasing sequence
3:1 N/A N/A N/A N/A
0 Core_pll_locked Locked of fPLL for link_clk and frame_clk. RO 1’b1