AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

ID 683317
Date 6/08/2022
Public Cortex-A9 MPU Address Maps

This section describes the address maps, as seen from the ARM Cortex-A9 microprocessor unit (MPU) subsystem side.
Table 2.  HPS-to-FPGA Address Map
Peripheral Address Offset Size (Bytes) Description
jesd204b_rx_control_0 0x0 4M Stores one channel RX channel data, only 1M physical memory is implemented, read only.
jesd204b_rx_control_0 0x40_0000 256K Stores one channel TX channel data, write only.
Table 3.  Lightweight HPS-to-FPGA Address MapThis table lists the memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address of 0xFF20_0000.
Peripheral Address Offset Size (Bytes) Description
sysid_qsys 0x0000_0000 8

sysid_qsys[23:0]: Project version register. Format: yymmdd. For example, 200411 means 2020, April, 11.

sysid_qsys[31:24]: ID flag of JESD204B and JESD204C. For example, 0xD9 means JESD204B and 0xDA means JESD204C.

spi_cs_pio 0x0000_1000 0x1f Uses GPIO as chip select signal of SPI bus.
pio_module_0 0x0000_2000 0x1ff Implements two registers at module offset 0x4 and 0x100 to implement specific register required by ADI ADRV9029 Sub6G EB board.
pio_module_gpio12_0 0x0000_3000 0x1ff Implements REFE GPIO register at offset 0x20, [11:0] is valid.
Transceiver reconfiguration 0x0001_0000 0x4000 SERDES calibration.
Base_address_reset_seq 0x0001_4800 N/A Resets sequence IP to JESD204B subsystem.
Fpll_core_pll_reconfiguration 0x0001_9000 N/A fPLL calibration.
SERDES ATX PLL reconfiguration 0x0001_a000 N/A SERDES ATX PLL calibration.
Base_address_control_pio 0x0001_8020 N/A Refer to control register description.
Base_address_status_pio 0x0001_8040 N/A Status register.
Base_address_status_pll 0x0001_8060 N/A PLL status register.
Base_address_sample_control 0x000f_0040 N/A Sample control register.