AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

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ID 683317
Date 6/08/2022
Public
Document Table of Contents
Document Table of Contents x
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board x
1.1. Introduction 1.2. Hardware and Software Requirements 1.3. Hardware Design 1.4. Functional Description 1.5. Reference Design 1.6. Document Revision History for AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board 1.7. Appendix
1.4. Functional Description x
1.4.1. DFE Processing in FPGA 1.4.2. JESD204B Subsystem Overview
1.5. Reference Design x
1.5.1. Design Files 1.5.2. Running the Demo with Prebuilt Binaries 1.5.3. Enable Loopback 1.5.4. Configuration Registers
1.5.2. Running the Demo with Prebuilt Binaries x
1.5.2.1. Bringing Up Demo System Using SD Card Image
1.5.2.1. Bringing Up Demo System Using SD Card Image x
1.5.2.1.1. Creating SD Card 1.5.2.1.2. Configuring the Board 1.5.2.1.3. Running the Demo
1.5.4. Configuration Registers x
1.5.4.1. Address Map 1.5.4.2. Status Registers 1.5.4.3. Control Registers 1.5.4.4. PLL Status Registers 1.5.4.5. Base_address_sample_control Registers
1.5.4.1. Address Map x
1.5.4.1.1. Cortex-A9 MPU Address Maps
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

1.3. Hardware Design

Figure 1. System Diagram
  • The ADI ADRV9029 Sub6G EBZ board has four slave devices.
  • The SPIM0 master controller is enabled and exported to the FPGA fabric and then connected to the ADI ADRV9029 Sub6G EBZ board through the J19 FMC connector.
  • A general purpose I/O (GPIO) module is instantiated and implemented the serial peripheral interface (SPI) chip select (CS). The module name is spi_cs_pio. Another two GPIO modules are instantiated and implements the GPIO function required by the ADI ADRV9029 Sub6G EBZ board. One module name is pio_module_0, and the other module name is pio_module_gpio12_0. The SYS ID module is used to save project version info.
  • The I2C1 controller connects to flash on the ADI ADRV9029 Sub6G EBZ board using device address 0x52.
  • The JESD204B subsystem includes both digital front end (DFE) processing and JESD204B Intel® FPGA IP, with the transceiver reconfiguration feature enabled. 4 SERDES channels are implemented in this project and are connected to the ADI ADRV9029 Sub6G EBZ board through the J19 FPGA mezzanine card (FMC) connector.
  • The jesd204b_rx_fifo_0 subsystem includes a memory block that stores source data, data reading function and data processing logic in the transmitter (TX) direction. In the receiver (RX) direction, one memory block is instantiated to save channel data and allows the central processing unit (CPU) to read and send to the host PC graphical user interface (GUI) software.
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