AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

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ID 683317
Date 6/08/2022
Public
Document Table of Contents
Document Table of Contents x
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board x
1.1. Introduction 1.2. Hardware and Software Requirements 1.3. Hardware Design 1.4. Functional Description 1.5. Reference Design 1.6. Document Revision History for AN 934: Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board 1.7. Appendix
1.4. Functional Description x
1.4.1. DFE Processing in FPGA 1.4.2. JESD204B Subsystem Overview
1.5. Reference Design x
1.5.1. Design Files 1.5.2. Running the Demo with Prebuilt Binaries 1.5.3. Enable Loopback 1.5.4. Configuration Registers
1.5.2. Running the Demo with Prebuilt Binaries x
1.5.2.1. Bringing Up Demo System Using SD Card Image
1.5.2.1. Bringing Up Demo System Using SD Card Image x
1.5.2.1.1. Creating SD Card 1.5.2.1.2. Configuring the Board 1.5.2.1.3. Running the Demo
1.5.4. Configuration Registers x
1.5.4.1. Address Map 1.5.4.2. Status Registers 1.5.4.3. Control Registers 1.5.4.4. PLL Status Registers 1.5.4.5. Base_address_sample_control Registers
1.5.4.1. Address Map x
1.5.4.1.1. Cortex-A9 MPU Address Maps
1. Using Flexible Radio Platform with Intel® Arria® 10 FPGA and ADI ADRV9029 Sub6G EBZ Board

1.5.4.5. Base_address_sample_control Registers

Table 7.  Base_address_sample_control RegisterAddress: 0xff2f0040
Bit Register Name Description Attribute Reset Value
5:4 Rx sample channel select
  • 0-channel 0
  • 1-channel 1
  • 2-channel 2
  • 3-channel 3
 N/A 2’b00
2 Tx customer data enable Sets to 1 to bypass DL signal process modules. N/A 1’b0
0 Rx sample enable Sets bit[0] to 1 trigger sampling RX channel data and write to RX memory. N/A 1’b0
Level Two Title