| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.4 |
| IP Version 20.3.0 |
The Low Latency 100G Ethernet Intel Agilex FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the Intel® Quartus® Prime IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
The Low Latency 100G Ethernet Intel Agilex FPGA IP supports design example generation with a wide range of parameters. However, the design examples do not cover all possible parameterizations of the Low Latency 100G Ethernet Intel Agilex FPGA IP Core.