Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

ID 683315
Date 12/14/2020

1.5. Compiling and Configuring the Design Example in Hardware

The Intel® FPGA IP core parameter editor allows you to compile and configure the design example on a target development kit.
To compile and configure a design example on hardware, follow these steps:
  1. Launch the Intel® Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
  2. After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Intel device:
    1. Select Tools > Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Intel® Agilex™ device to your Intel® Quartus® Prime Pro Edition session.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Turn on Program/Configure option for the .sof.
    9. Click Start.