Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

ID 683315
Date 12/14/2020

1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware

After you compile the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP core design example and configure it on your Intel device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  2. In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
  3. Type source main.tcl to open a connection to the JTAG master.
Additional design example commands are available to program the IP core:
  • chkphy_status: Displays the clock frequencies and PHY lock status.
  • chkmac_stats: Displays the values in the MAC statistics counters.
  • clear_all_stats: Clears the IP core statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • sys_reset_digital_analog: System reset.
  • loop_on: Turns on internal serial loopback
  • loop_off: Turns off internal serial loopback.
  • reg_read <addr>: Returns the IP core register value at <addr>.
  • reg_write <addr> <data>: Writes <data> to the IP core register at address <addr>.
Follow the test procedure in the Hardware Testing section of the design example and observe the test results in the System Console.