Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide
ID
683315
Date
12/14/2020
Public
1.1. Generating the Design Example
1.2. Directory Structure
1.3. Simulating the Design Example Testbench
1.4. Compiling the Compilation-Only Project
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware
2.5.1. Packet Generator Programming Sequence
You can initiate the packet transmission from the packet generator to the IP core by programming Packet Size Configure, Packet Number Control, and PKT_GEN_TX_CTRL registers.
The programming sequence varies based on a selected mode PKT_GEN_TX_CTRL[5:4]:
In Random Mode:
- Set Packet Number Control[31] to 0.
- Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
- Set PKT_GEN_TX_CTRL[1] to 1 to stop the packet generator.
In Fixed/Incremental Mode—with fixed number of packets:
- Configure Packet Size Configure.
- Configure the number of packets: Bit [31] must be set to specify Packet Number Control[30:0]
- Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
- The packet generator stops when the number of packets reaches 0.
In Fixed/Incremental Mode— without fixed number of packets:
- Configure Packet Size Configure.
- Set Packet Number Control[31] to 0.
- Set PKT_GEN_TX_CTRL[1] to 0 to start the packet transmission through the packet generator.
- Set PKT_GEN_TX_CTRL[1] to 1 to stop the packet generator.