Low Latency 100G Ethernet Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683315
Date 12/14/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling the Compilation-Only Project 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
1.6. Testing the Low Latency 100G Ethernet Intel Agilex FPGA Intel® FPGA IP Design in Hardware x
1.6.1. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Simulation 2.4. Design Example Behavior 2.5. Design Example Registers 2.6. Design Example Interface Signals
2.5. Design Example Registers x
2.5.1. Packet Generator Programming Sequence
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 100G Ethernet Intel Agilex FPGA IP Design Example User Guide

1.1. Generating the Design Example

Figure 2. Procedure
Figure 3. Example Design Tab in the Low Latency 100G Ethernet Intel Agilex FPGA IP Parameter Editor
  1. If you do not already have an Intel® Quartus® Prime Pro Edition project in which to integrate your Low Latency 100G Ethernet Intel Agilex FPGA IP core, you must create one.
    1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
    2. Specify the device family Agilex (F-Series/I-Series) and select a device that meets all of these requirements:
      • Transceiver tile is H-tile
      • Transceiver speed grade is –1 or –2
      • Core speed grade is –1 or –2
      • Device: AGFB014R17A2E2V
    3. Click Finish.
  2. In the IP Catalog, locate and select Low Latency 100G Ethernet Intel Agilex FPGA . The New IP Variation window appears.
  3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation.
    Note: Enable TX CRC insertion and Enable RX/TX statistics counters parameters are enabled by default.
  6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the compilation-only and hardware design examples.
    Note: You must select at least one of the Simulation and Synthesis options to generate the design example.
  7. On the Example Design tab, under Generated HDL Format, only Verilog HDL is available. This IP core does not support VHDL.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.
  9. If you want to modify the design example directory path or name from the defaults displayed (alt_e100fmh_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).

Section Content
Design Example Parameters

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