Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Document Table of Contents

Low Latency Ethernet 10G MAC IP Core v14.1

Table 23.  v14.1 December 2014
Description Impact
Added new parameter options:
  • Enable 10GBASE-R register mode
  • Time of Day Format.
If you do not upgrade your IP core, it does not have this new feature.
Added new signals to support 10GBASE-R register mode:
  • tx_xcvr_clk
  • rx_xcvr_clk
  • xgmii_tx_valid
  • xgmii_rx_valid