Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v5.1.0
Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v5.0.0
Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v4.0.0
Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v3.0.0
Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v2.1.0
Low Latency Ethernet 10G MAC IP (intel_eth_em10g32) v2.0.0
Low Latency Ethernet 10G MAC IP v22.2.0
Low Latency Ethernet 10G MAC IP v22.0.4
Low Latency Ethernet 10G MAC IP v22.0.3
Low Latency Ethernet 10G MAC IP v22.0.1
Low Latency Ethernet 10G MAC IP v22.0.0
Low Latency Ethernet 10G MAC IP v20.1.0
Low Latency Ethernet 10G MAC IP v20.0.0
Low Latency Ethernet 10G MAC IP v19.3.1
Low Latency Ethernet 10G MAC IP v19.3.0
Low Latency Ethernet 10G MAC IP v19.2.0
Low Latency Ethernet 10G MAC IP v19.1
Low Latency Ethernet 10G MAC IP v18.1
Low Latency Ethernet 10G MAC IP v18.0
Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1
Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1
Low Latency Ethernet 10G MAC IP Core v17.0
Low Latency Ethernet 10G MAC IP Core v16.1
Low Latency Ethernet 10G MAC IP Core v16.0
Low Latency Ethernet 10G MAC IP Core v15.1
Low Latency Ethernet 10G MAC IP Core v15.0
Low Latency Ethernet 10G MAC IP Core v14.1
Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition
Low Latency Ethernet 10G MAC IP Core v14.0
Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition
Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC IP v22.2.0
| Quartus® Prime Version | Description | Impact |
|---|---|---|
| 24.2 | Added support for signal tap debugging for 10M/100M/1G/2.5G/5G/10G (USXGMII) design example for Agilex™ 7 (F-Tile) devices. | — |