Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

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ID 683308
Date 4/01/2024
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Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v2.0.0
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.3 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.1.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.2.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Low Latency Ethernet 10G MAC IP Core v17.0 Low Latency Ethernet 10G MAC IP Core v16.1 Low Latency Ethernet 10G MAC IP Core v16.0 Low Latency Ethernet 10G MAC IP Core v15.1 Low Latency Ethernet 10G MAC IP Core v15.0 Low Latency Ethernet 10G MAC IP Core v14.1 Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v14.0 Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes

Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1

Table 15.  v17.1 November 2017
Description Impact
Added support for the Cyclone® 10 GX device family. This device is only available in Quartus® Prime software version 17.1 onwards.
Added support for the following operation modes for Stratix® 10 devices:
  • 10/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G
—
Added a new feature—Peer-to-Peer:
  • Added a new parameter—Enable peer-to-peer support.
  • Added new timestamp registers:
    • Added new IEEE 1588v2 Egress TX signals—tx_egress_p2p_update and tx_egress_p2p_val[].
    • Added new IEEE 1588v2 Ingress RX signals—rx_ingress_p2p_val[] and rx_ingress_p2p_val_valid.
These changes are optional. If you do not upgrade your IP core, it does not have these new features.
You cannot turn on the Enable ECC on memory blocks parameter with the Enable time stamping parameter. The IP core may not exhibit the expected behavior when both parameters are turned on at the same time. This is applicable in Quartus® Prime Pro Edition and Quartus® Prime Standard Edition version 17.0 and earlier.
Design Examples for Low Latency 10G Ethernet MAC:
  • Added the following design examples for Stratix® 10 devices:
    • 10M/100M/1G/2.5G/10G Ethernet
    • 1G/2.5G Ethernet with IEEE 1588v2
    • 1G/2.5G/10G Ethernet with IEEE 1588v2
    • 10G USXGMII Ethernet
 —

In previous versions of the Low Latency Ethernet 10G MAC design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Quartus® Prime version 17.1.

If you are upgrading designs that have these additional constraints from the previous versions of Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information.
10GBASE-R register mode is not supported in Stratix® 10 devices. —
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