Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

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ID 683308
Date 12/19/2022
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Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.1.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.2.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Low Latency Ethernet 10G MAC IP Core v17.0 Low Latency Ethernet 10G MAC IP Core v16.1 Low Latency Ethernet 10G MAC IP Core v16.0 Low Latency Ethernet 10G MAC IP Core v15.1 Low Latency Ethernet 10G MAC IP Core v15.0 Low Latency Ethernet 10G MAC IP Core v14.1 Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v14.0 Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1

Table 7.  v19.1 April 2019
Description Impact
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint. —
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