Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 12/19/2022
Public

Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1

Table 7.  v19.1 April 2019
Description Impact
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint.

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