AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

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ID 683299
Date 2/18/2019
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Document Table of Contents
Document Table of Contents x
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software x
1.1. Features 1.2. Overview 1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core 1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software 1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software 1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer 1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.8. Intel® FPGA Serial Flash Loader IP Core Parameter 1.9. Intel® FPGA Serial Flash Loader IP Core Signals 1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software x
1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software x
1.5.1. Converting .sof to .jic Files in the Intel® Quartus® Prime Software 1.5.2. Converting .jic Files to .jam Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer x
1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files 1.6.2. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jam Files
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.7.1. Multiple Configuration Devices Support 1.7.2. Boot Page Selection
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

1.2. Overview

Figure 1. In-System Programming MethodThis figure shows the in-system programming method using the Intel® FPGA Serial Flash Loader IP core.


Table 1.  In-System Programming Method BlocksThis table lists the blocks in the in-system programming method using the Intel® FPGA Serial Flash Loader IP core.
Block Description
JTAG This block refers to the FPGA internal JTAG hard logic.
Intel® FPGA Serial Flash Loader IP core The IP core instantiates serial flash loader (SFL) image into your design to bridge the JTAG and ASMI interfaces. This feature allows you to perform SFL programming without resetting your design in the FPGA.
ASMI This block is the FPGA internal ASMI hard logic.
Serial Configuration Device This block refers to the following serial configuration devices:
  • EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128.
  • EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256.
  • EPCQL256, EPCQL512, and EPCQL1024.
  • EPCQ4A, EPCQ16A, EPCQ32A, EPCQ64A, EPCQ128A, and EPCQ512A.
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