AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

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ID 683299
Date 2/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software x
1.1. Features 1.2. Overview 1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core 1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software 1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software 1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer 1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.8. Intel® FPGA Serial Flash Loader IP Core Parameter 1.9. Intel® FPGA Serial Flash Loader IP Core Signals 1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software x
1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software x
1.5.1. Converting .sof to .jic Files in the Intel® Quartus® Prime Software 1.5.2. Converting .jic Files to .jam Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer x
1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files 1.6.2. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jam Files
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.7.1. Multiple Configuration Devices Support 1.7.2. Boot Page Selection
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core

You must create an instance of the Intel® FPGA Serial Flash Loader IP core in your FPGA top-level design. To create the instance of the Intel® FPGA Serial Flash Loader IP core, follow these steps:
  1. In the IP Catalog window, search for and click Intel® FPGA Serial Flash Loader. Click Add. The IP Parameter Editor appears.
  2. In the New IP Instance dialog box, specify your top-level file name.
  3. Turn on the Share ASMI interface in your design parameter if you must share the ASMI interface with your design. This option provides additional control pins for controlling the ASMI interface to access external serial configuration device from core logic.
  4. Click Finish to instantiate the Intel® FPGA Serial Flash Loader IP core.
    Note: The Intel® FPGA Serial Flash Loader IP core does not have any timing or simulation model. Therefore, you cannot simulate the IP core.
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