AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

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ID 683299
Date 2/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software x
1.1. Features 1.2. Overview 1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core 1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software 1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software 1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer 1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 1.8. Intel® FPGA Serial Flash Loader IP Core Parameter 1.9. Intel® FPGA Serial Flash Loader IP Core Signals 1.10. Document Revision History for AN 370: Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software
1.4. Using the Intel® FPGA Serial Flash Loader IP Core in the Intel® Quartus® Prime Software x
1.4.1. Instantiating the Intel® FPGA Serial Flash Loader IP Core
1.5. Generating .jic and .jam Programming Files in the Intel® Quartus® Prime Software x
1.5.1. Converting .sof to .jic Files in the Intel® Quartus® Prime Software 1.5.2. Converting .jic Files to .jam Files in the Intel® Quartus® Prime Software
1.6. Programming Serial Configuration Devices with the Intel® Quartus® Prime Programmer x
1.6.1. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jic Files 1.6.2. Programming Serial Configuration Devices Using the Intel® Quartus® Prime Programmer and .jam Files
1.7. Features for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
1.7.1. Multiple Configuration Devices Support 1.7.2. Boot Page Selection
1. Using the Intel® FPGA Serial Flash Loader IP Core with the Intel® Quartus® Prime Software

1.3. Programming Single and Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core

To program serial configuration devices using the Intel® FPGA Serial Flash Loader IP core, set up your board in AS mode and then follow these steps:

  1. To bridge the JTAG interface to the active serial interface, configure the SFL image into the FPGA.
    Note: Bypass this step if the SFL image exists in the FPGA.
  2. Program the serial configuration device or devices through the JTAG-ASMI bridge of the SFL.
    Note: Programming serial configuration device uses one data line only regardless of the active serial configuration mode chosen.
  3. Reconfigure your FPGA with the new configuration data you programmed into the serial configuration device in Step 2. This replaces the SFL image with the new configuration data. To reconfigure the FPGA with the new configuration data, pull the nConfig pin low and then release the pin.
    Note: You can include the Intel® FPGA Serial Flash Loader IP core in your new configuration data to allow programming the serial configuration device when your FPGA is in user mode.
Figure 2. Programming Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core Programming FlowThis figure shows the general programming flow to program serial configuration devices with the Intel® FPGA Serial Flash Loader IP core.


Figure 3. Programming a Single Serial Configuration Device with the Intel® FPGA Serial Flash Loader IP Core Programming FlowThis figure shows the programming flow to program a single serial configuration device with the Intel® FPGA Serial Flash Loader IP core.


Figure 4. Programming Multiple Serial Configuration Devices with the Intel® FPGA Serial Flash Loader IP Core Programming FlowThis figure shows the programming flow to program multiple serial configuration devices with the Intel® FPGA Serial Flash Loader IP core.


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