AN 370: Using the Intel FPGA Serial Flash Loader with the Intel Quartus Prime Software

ID 683299
Date 2/18/2019
Public
Document Table of Contents

1.8. Intel® FPGA Serial Flash Loader IP Core Parameter

Table 3.   Intel® FPGA Serial Flash Loader IP Core Parameter
Parameter Value Description
Share ASMI interface with your design Turn On, Turn Off Turn on the Share ASMI interface in your design parameter if you must share the ASMI interface with your FPGA design. This option provides additional control pins for controlling the ASMI interface to access external serial configuration device from core logic.
Use enhanced mode SFL Turn On, Turn Off The Use enhanced mode SFL parameter is enabled by default. This option provides more flexibility for JTAG cascading environment and the usage of the SFL with a third-party programmer tool. Turn off the Use enhanced mode SFL parameter if you do use enhanced SFL.

For Arria® V, Arria® V GZ, Intel® Arria® 10, Intel® Cyclone® 10 GX, Cyclone® V, and Stratix® V devices, you cannot disable this parameter.