IOPLL Intel® FPGA IP Core User Guide

ID 683285
Date 2/06/2023

Reference Clock Switchover

The reference clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy, or for a dual clock domain application such as in a system. The system can turn on a redundant clock if the primary clock stops running.

Using the reference clock switchover feature, you can specify the frequency for the second input clock, and select the mode and delay for the switchover.

The clock loss detection and reference clock switchover block has the following functions:

  • Monitors the reference clock status. If the reference clock fails, the clock automatically switches to a backup clock input source. The clock updates the status of the clkbad and activeclk signals to alert the event.
  • Switches the reference clock back and forth between two different frequencies. Use the extswitch signal to manually control the switch action. After a switchover occurs, the PLL may lose lock temporarily and go through the reckoning process.