IOPLL IP Core Parameters - PLL Tab
|Device Family||Intel® Arria® 10 , Intel® Cyclone® 10 GX||Specifies the device family.|
|Component||—||Specifies the targeted device.|
|Speed Grade||—||Specifies the speed grade for targeted device.|
|PLL Mode||Integer-N PLL||Specifies the mode used for the IOPLL IP core. The only legal selection is Integer-N PLL. If you need a fractional PLL, you must use the fPLL Intel Arria 10/Cyclone 10 FPGA IP core.|
|Reference Clock Frequency||—||Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum value is dependent on the selected device.|
|Enable Locked Output Port||Turn on or Turn off||Turn on to enable the locked port.|
|Enable physical output clock parameters||Turn on or Turn off||Turn on to enter physical PLL counter parameters instead of specifying a desired output clock frequency.|
|Operation Mode||direct, external feedback, normal, source synchronous, zero delay buffer, or lvds||Specifies the operation of the PLL. The default operation is direct mode.
|Number of Clocks||1–9||Specifies the number of output clocks required for each device in the PLL design. The requested settings for output frequency, phase shift, and duty cycle are shown based on the number of clocks selected.|
|Specify VCO Frequency||Turn on or Turn off||Allows you to restrict the VCO frequency to the specified value. This is useful when creating a PLL for LVDS external mode, or if a specific dynamic phase shift step size is desired.|
|VCO Frequency 1||—||
|Give clock global name||Turn on or Turn off||Allows you to rename the output clock name.|
|Clock Name||—||The user clock name for Synopsis Design Constraints (SDC).|
|Desired Frequency||—||Specifies the output clock frequency of the corresponding output clock port, outclk, in MHz. The default value is 100.0 MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.|
|Actual Frequency||—||Allows you to select the actual output clock frequency from a list of achievable frequencies. The default value is the closest achievable frequency to the desired frequency.|
|Phase Shift units||ps or degrees||Specifies the phase shift unit for the corresponding output clock port, outclk, in picoseconds (ps) or degrees.|
|Desired Phase Shift||—||Specifies the requested value for the phase shift. The default value is 0 ps.|
|Actual Phase Shift||—||Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.|
|Desired Duty Cycle||0.0–100.0||Specifies the requested value for the duty cycle. The default value is 50.0%.|
|Actual Duty Cycle||—||Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle.|
|Multiply Factor (M-Counter) 2||4–511||
Specifies the multiply factor of M-counter.
The legal range of the M counter is 4–511. However, restrictions on the minimum legal PFD frequency and maximum legal VCO frequency restrict the effective M counter range to 4–160.
|Divide Factor (N-Counter) 2||1–511||
Specifies the divide factor of N-counter.
The legal range of the N counter is 1–511. However, restrictions on the minimum legal PFD frequency restrict the effective range of the N counter to 1–80.
|Divide Factor (C-Counter) 2||1-511||Specifies the divide factor for the output clock (C-counter).|
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