IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 2/06/2023
Public

IOPLL IP Core Parameters - Cascading Tab

Table 3.   IOPLL IP Core Parameters - Cascading Tab
Parameter Legal Value Description
Create a ‘cascade out’ signal to connect with a downstream PLL Turn on or Turn off Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL.
Specifies which outclk to be used as cascading source 0-8 Specifies the cascading source.
Create an adjpllin or cclk signal to connect with an upstream PLL Turn on or Turn off Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL.
Level Two Title