IOPLL Intel® FPGA IP Core User Guide

ID 683285
Date 2/06/2023
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PLL Lock

The PLL lock is dependent on the two input signals in the phase frequency detector. The lock signal is an asynchronous output of the PLLs.7

The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to calculate the number of clock cycles required to gate the lock signal.

7 Timing analyzer may report the PLL lock signal as synchronous due to the signal being in the same clock domain as the reference clock signal. However, the PLL lock signal is designed to be an asynchronous signal with the addition of a synchronizer.