IOPLL Intel® FPGA IP Core User Guide

ID 683285
Date 2/06/2023

PLL-to-PLL Cascading

If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the cascaded PLLs may amplify phase noise at certain frequencies.

The adjpllin input clock source is used for inter-cascading between fracturable fractional PLLs.

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