IOPLL Intel® FPGA IP Core User Guide

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ID 683285
Date 6/24/2019
Public

IOPLL Intel® FPGA IP Core User Guide

Updated for:
Intel® Quartus® Prime Design Suite 18.1
The IOPLL Intel® FPGA IP core allows you to configure the settings of the Intel® Arria® 10 and Intel® Cyclone® 10 GX I/O PLL.

IOPLL IP core supports the following features:

  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to nine clock output signals for the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
  • Switches between two reference input clocks.
  • Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL cascading mode.
  • Generates the Memory Initialization File (.mif) and allows PLL dynamic reconfiguration.
  • Supports PLL dynamic phase shift.

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