Customizable Flash Programmer User Guide

ID 683271
Date 4/28/2023
Document Table of Contents
Give Feedback Configuring Generic Serial Flash Interface IP Core

The Generic Serial Flash Interface IP core is only available in the Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition software version 18.0 and later. You can instantiate this IP core from the Platform Designer IP Catalogue.

Intel recommends setting the Device Density (Mb) to 2048 even if you are using a lower device density. This setting may support any density lower than 2048 Mb.

Note: If the value for the Device Density (Mb) is changed, the base address of your Avalon® -MM register maps deviates from the default base address defined in the TCL script. If you need to change to other device density, you need to match the base address defined in the TCL script to the Platform Designer Avalon® -MM base address.

You can set the Number of Chip Selects used up to 3. Only Intel® Arria® 10 and Intel® Cyclone® 10 GX support cascaded flash. If you set this value to 3 for other FPGAs, ensure the first chip is always selected during flash access.