Customizable Flash Programmer User Guide

ID 683271
Date 4/28/2023
Public
Document Table of Contents
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3.1.1. Understanding Quad SPI Flash Byte-Addressing

The flash devices usually support one or both of the following byte-addressing modes:

  • 3-byte addressing
  • 4-byte addressing
Note: Refer to the third-party quad SPI flash datasheet for the byte-addressing modes supported for your flash devices.

The flash device reads either 24-bit (3-byte) address or 32-bit (4-byte) address before the flash device starts taking data to write to the flash memory, or output the data if the flash device receives a read command.

Figure 2. Reading Configuration Data from Flash with 3-Byte and 4-Byte Addressing
Table 2.  Byte-Addressing Requirement for Intel FPGAs
FPGA Devices Required Power Up Byte-Addressing of the Flash Devices
Legacy device older than 28nm devices, Intel® Cyclone® 10 LP 3-byte addressing
Cyclone® V, Arria® V, Stratix® V
  • 3-byte addressing (limited memory address access)
  • 4-byte addressing
Intel® Arria® 10, Intel® Cyclone® 10 GX 4-byte addressing

For example, if your flash device does not support power up 4-byte addressing mode, you cannot use your flash device for the Intel® Arria® 10 and Intel® Cyclone® 10 GX configuration.

Flash devices with density more than 128 megabits (Mb) require 4-byte address to access the memory space higher than 128 Mb. For flash devices that do not support non-volatile 4-byte addressing setting, the FPGA is unable to read the configuration image that has the start address beyond 128 Mb and unable to store image beyond 128Mb for Remote System Update application.

Figure 3. Memory Space of a 256 Mb Flash