Customizable Flash Programmer User Guide

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ID 683271
Date 4/28/2023
Public
Document Table of Contents
Document Table of Contents x
1. Customizable Flash Programmer Overview 2. Customizable Flash Programmer 3. Implementing the Customizable Flash Programmer 4. Document Revision History for the Customizable Flash Programmer User Guide
1. Customizable Flash Programmer Overview x
1.1. Device Family Support 1.2. Software Support
2. Customizable Flash Programmer x
2.1. Programmer Image 2.2. System Console TCL Script 2.3. Limitations and Restrictions
3. Implementing the Customizable Flash Programmer x
3.1. Generating the Raw Programming Data File (.rpd) from User Design 3.2. Compiling the Programmer Image Project and Generating the .sof File 3.3. Customizing the TCL Script 3.4. Programming the Flash Using the System Console
3.1. Generating the Raw Programming Data File (.rpd) from User Design x
3.1.1. Understanding Quad SPI Flash Byte-Addressing 3.1.2. Understanding Dummy Clock Cycles for Single and Quad IO Fast Read 3.1.3. Generating the .rpd File Using the Convert Programming File Tool
3.1.3. Generating the .rpd File Using the Convert Programming File Tool x
3.1.3.1. Generating .rpd File for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 3.1.3.2. Generating .rpd File for Other FPGA Devices
3.2. Compiling the Programmer Image Project and Generating the .sof File x
3.2.1. Configuring the IP Cores Setting 3.2.2. Assigning External Clock Source for the IP Cores 3.2.3. Generating the Programmer Image .sof File from the Reference Project
3.2.1. Configuring the IP Cores Setting x
3.2.1.1. Configuring JTAG to Avalon® Master Bridge IP Core 3.2.1.2. Configuring Intel AvMM Bursting Master IP Core 3.2.1.3. Configuring Generic Serial Flash Interface IP Core
3.3. Customizing the TCL Script x
3.3.1. TCL Script Structures 3.3.2. TCL Script User Setting 3.3.3. Customizing the Programming Flow 3.3.4. Creating Custom Functions
3.4. Programming the Flash Using the System Console x
3.4.1. Executing Commands in the System Console 3.4.2. Executing the System-Console Commands in the Nios® II Command Shell
1. Customizable Flash Programmer Overview
2. Customizable Flash Programmer
3. Implementing the Customizable Flash Programmer
4. Document Revision History for the Customizable Flash Programmer User Guide

3.2.1.2. Configuring Intel AvMM Bursting Master IP Core

The Intel AvMM Bursting Master IP core is a custom IP core developed to trigger burst write to or burst read from the Generic Serial Flash Interface IP core.

The following files are located in the Intel® Quartus® Prime project folder:

  • intel_avmm_bursting_master_hw.tcl
  • intel_avmm_bursting_master.sv
  • altera_avalon_sc_fifo_export_fill_lel.sv

Ensure the three files are located in the project folder correctly. Instantiate this IP core in the Platform Designer environment. You can find the IP core in the IP Catalog: Project > Peripherals > Debug and Performance > Intel AvMM Bursting Master .

Table 4.  Recommended Settings for Intel AvMM Bursting Master IP Core
Properties Setting Description
General Master Properties
Master Address Width 28 – 256M Bytes Support up to 2 Gb flash density.
Master Data Width — This setting is not applicable.
byteenable Width — This setting is not applicable.
Master is Pipelined? — This setting is not applicable.
Burst Specific Properties
burstcount Width 7 – 64 Words Page Write usually takes up to 256 bytes or 64 words per transaction., Certain flash devices may accept more bytes per Page Write transaction.
Master Users Bursts? BURST Set to burst mode.
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