DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

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ID 683270
Date 8/03/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the DMA AFU Example 7. Simulating the AFU Example 8. Optimization for Improved DMA Performance 9. DMA Accelerator Functional Unit User Guide Archives 10. Document Revision History for the DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space 3.1.2. Device Feature Header Linked-List
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the DMA AFU Example
7. Simulating the AFU Example
8. Optimization for Improved DMA Performance
9. DMA Accelerator Functional Unit User Guide Archives
10. Document Revision History for the DMA Accelerator Functional Unit User Guide

2.1. Introduction

The Direct Memory Access (DMA) AFU example shows how to manage memory transfers between the host processor and the FPGA. You can integrate the DMA AFU into your design to move data between the host memory and the FPGA local memory.

The DMA AFU comprises the following submodules:

  • Memory Properties Factory (MPF) Basic Building Block (BBB)
  • Core Cache Interface (CCI-P) to the Avalon® Memory-Mapped ( Avalon® -MM) Adapter
  • DMA Test System which contains the DMA BBB

These submodules are described in more detail in the DMA AFU Hardware Components topic below.

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