DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

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ID 683270
Date 8/03/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the DMA AFU Example 7. Simulating the AFU Example 8. Optimization for Improved DMA Performance 9. DMA Accelerator Functional Unit User Guide Archives 10. Document Revision History for the DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space 3.1.2. Device Feature Header Linked-List
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the DMA AFU Example
7. Simulating the AFU Example
8. Optimization for Improved DMA Performance
9. DMA Accelerator Functional Unit User Guide Archives
10. Document Revision History for the DMA Accelerator Functional Unit User Guide

10. Document Revision History for the DMA Accelerator Functional Unit User Guide

Document Version Intel® Acceleration Stack Version Changes
2020.08.03 2.0.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2) Corrected the AF image file name in section Compiling the DMA AFU Example.
2020.04.17 2.0.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2) Corrected a statement in Intended Audience section.
2020.02.20 2.0.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2) Fixed typo.
2019.11.04 2.0.1 (supported with Intel® Quartus® Prime Pro Edition Edition 19.2)
  • Replaced the fpgaconf with fpgasupdate when configuring the FPGA with the prebuild AFU in section Running the DMA AFU Example.
  • Added subtitle Intel® FPGA Programmable Acceleration Card D5005 to the document title.
  • Added environment variable $OPAE_PLATFORM_ROOT.
  • Modified section Software Programming Model for minor edits.
  • Added new section Compiling the DMA AFU Example.
  • Modified section Optimization for Improved DMA Performance for minor edits.
2019.08.05 2.0 (supported with Intel Quartus Prime Pro Edition 18.1.2) Initial release.
Level Two Title