DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

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ID 683270
Date 8/03/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the DMA AFU Example 7. Simulating the AFU Example 8. Optimization for Improved DMA Performance 9. DMA Accelerator Functional Unit User Guide Archives 10. Document Revision History for the DMA Accelerator Functional Unit User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space 3.1.2. Device Feature Header Linked-List
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the DMA AFU Example
7. Simulating the AFU Example
8. Optimization for Improved DMA Performance
9. DMA Accelerator Functional Unit User Guide Archives
10. Document Revision History for the DMA Accelerator Functional Unit User Guide

3.1. DMA AFU Register Map

The DMA AFU register map provides the absolute addresses of all the locations within the unit. These registers are in the host view because it's only the host that can access them.

Table 4.  DMA AFU Memory Map
Byte Address Offsets Name Span in Bytes Description
0x0 DMA AFU DFH 0x40 Device feature header for the DMA AFU. The ID_L is set to 0x9081f88b8f655caa and ID_H is set to 0x331db30c988541ea. The DMA AFU DFH has been parameterized to point to offset 0x100 to find the next DFH (DMA BBB DFH). You must not modify the base address of the DMA AFU DFH since it must be located at address 0x0 as defined by the CCIP specification.
0x100 DMA BBB 0x100 Specifies DMA BBB control and status register interface. You can refer to the DMA BBB register map for more information. Within the DMA BBB at offset 0 the DMA BBB includes it's own DFH. This DFH has been set to find the next DFH at offset 0x100 (NULL DFH). If you add more DMA BBBs, space them 0x100 apart and ensure the NULL DFH follows the last DMA by 0x100.
0x200 NULL DFH 0x40 Terminates the DFH linked-list. The ID_L is set to 0x90fe6aab12a0132f and ID_H is set to 0xda1182b1b3444e23. The NULL DFH has been parameterized to be the last DFH in hardware. For this reason the NULL DFH is located at address 0x200. If you add additional DMA BBBs to the system, you need to increase the NULL DFH base address accordingly so that it remains at the highest address. The DMA driver and test application do not use this hardware.

Table 5.  DMA BBB Memory MapThe following byte addresses are relative offsets from the DMA BBB base address in the DMA AFU system (0x100).
Byte Address Offsets Name Span in Bytes Description
0x0 DMA BBB DFH 0x40 Device feature header for the DMA AFU. The ID_L is set to 0xa9149a35bace01ea and ID_H is set to 0xef82def7f6ec40fc . The DMA BBB DFH has been parameterized to point to 0x100 for the next DFH offset. This next offset can be another DMA BBB, another DFH (not included in this design), or the NULL DFH.
0x40 Dispatcher 0x40 Control port for the dispatcher. The DMA driver uses this location to control the DMA or query its status.
0x80 Descriptor Frontend 0x40 The descriptor frontend is a custom component that reads descriptors from host memory and overwrites the descriptor when the DMA transfer completes. The driver instructs the frontend where the first descriptor lives in host memory and then the frontend hardware communicates with the driver primarily though descriptors stored in host memory.

Section Content
DMA AFU Address Space
Device Feature Header Linked-List

Level Two Title