DMA Accelerator Functional Unit User Guide: Intel® FPGA Programmable Acceleration Card D5005

ID 683270
Date 8/03/2020
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2.3.2. DMA BBB

The DMA BBB subsystem transfers data from source to destination addresses using Avalon® -MM transactions. The DMA driver controls the DMA BBB by accessing the control and status register of the various components inside the system. The DMA driver also controls the DMA BBB by using shared memory to communicate transfer descriptors. The DMA BBB accesses data in FPGA memory at offset 0x0. The DMA BBB accesses data and descriptors in host memory at offset 0x1_0000_0000_0000.

Figure 3. DMA BBB Platform Designer Block DiagramThis block diagram excludes some internal Pipeline Bridge IP cores.

The components in the DMA BBB Platform Designer implement the following functions:

  • Far Reach Bridge/Pipeline Bridge: A pipeline bridge with adjustable latency included to control topology and improve the design Fmax.
  • DMA BBB DFH: This is a device feature header for the DMA BBB. This DFH points to the next DFH located at offset 0x100 (Null DFH).
  • Descriptor Frontend: Responsible for fetching descriptors and transferring them to the Dispatcher. When a DMA transfer completes the frontend receives status information from the Dispatcher and overwrites the descriptor in host memory.
  • Dispatcher: This block schedules DMA transfers requests to the Read and Write Master.
  • Read Master: This block is responsible for reading data from host or local FPGA memory and sending it as streaming data to Write Master.
  • Write Master: This block is responsible for receiving streaming data from the Read Master and writing the contents to host or local FPGA memory.